Flip-flop circuit

ABSTRACT

To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a mater latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

CROSS-REFERENCE TO RELATED APPLICATION

This Nonprovisional application claims priority under 35 U.S.C. §119 (a)on Patent Application No. 2004-179954 filed in Japan on Jun. 17, 2004,the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention mainly relates to flip-flop circuits constitutedby transistors formed as semiconductor integrated circuits (LSIs).

Performances required of recent LSIs have been rapidly enhanced inrecent years, and LSI manufacturers have competed to achieve higherfunctionality and higher operation speed. LSI circuits for use insynchronous digital signal processing, for example, are designed to useflip-flop circuits as necessary components. Therefore, to achieve fasterLSI circuits, every manufacturer has to increase the speed of flip-flopcircuits.

In view of this, various configurations of flip-flop circuits for highspeed operation have been proposed to date. For example, a circuitconfiguration including a bypass circuit for allowing an input signal tobe output without change in addition to a master latch and a slave latchis known (see, for example, U.S. Pat. No. 5,656,962 (FIG. 5)).

More specifically, the flip-flop circuit includes: a master portion 205including a master latch; a slave portion 206 including a slave latch;and a bypass 207, as shown in FIG. 5 of this patent.

The master portion 205 includes a pass gate 310, an inverter 311 and aninverter 312. The master portion 205 holds data input from a data inputterminal 209 in synchronization with a clock signal input from a clocksignal input terminal while the clock signal is at an H (high) level.

The slave portion 206 holds data output from the master portion 205 andallows the data to be output via an inverter 315 and a pass gate 519while the clock signal is at an L (low) level.

The bypass 207 includes an inverter 316 and a pass gate 317. The bypass207 outputs data held in the master portion 205 while the clock signalis at the H (high) level.

That is, in the period after the clock signal has risen and before theclock signal falls, the pass gate 317 of the bypass 207 allows data topass through. On the other hand, in the period after the clock signalhas fallen and before the clock signal rises, the pass gate 519 of theslave portion 206 allows data to pass through and to be output from adata output terminal 208. In this manner, at the rising edge of theclock signal, data from the master portion 205 is output via the bypass207, which operates faster than the slave portion 206, thereby enablingthe data to be output from the data output terminal 208 in a short time.

In the conventional flip-flop circuit, however, physical characteristicsat the input and output terminal(s) 208 and/or 209 (i.e., an inputcapacitance with respect to the data input terminal 209 and/or an outputdriving capability with respect to the data output terminal 208) varydepending on the state of the clock signal. Therefore, the flip-flopcircuit has a drawback in which it is difficult to design and develop acircuit including such a flip-flop circuit in a short period.

Specifically, the input capacitance at the data input terminal 209 isdescribed as follows. When the clock signal is “1” (e.g., at the Hlevel), the pass gate 310 at the input of the master portion 205 isclosed. Accordingly, the input capacitance at the data input terminal209 is equal to the source capacitance of the pass gate 310. On theother hand, when the clock signal is “0” (e.g., at the L level), thepass gate 310 is open. Accordingly, the input capacitance at the datainput terminal 209 is equal to the sum of the source and draincapacitances of the pass gate 310, the gate capacitance of the inverter311, the gate capacitance of the inverter 316 and the drain capacitanceof the inverter 312, i.e., is different from that when the clock signalis “1”.

The driving capability at the data output terminal 208 is described asfollows. When the clock signal is “0”, the inverter 315 of the slaveportion 206 drives a subsequent circuit connected to the data outputterminal 208 (via the pass gate 519). On the other hand, when the clocksignal is “1”, the inverter 316 of the bypass 207 drives the subsequentcircuit (via the pass gate 317) with a driving capability different fromthat when the clock signal is “0”.

In recent LSI markets, rapid development of LSI circuits andintroduction thereof to the markets by using techniques allowingshort-term development are much more required than before. To achievethe short-term development of LSI circuits, a circuit design techniqueusing physical-characteristic-extracted data at a logic gate level(i.e., at the level of a circuit such as a flip-flop circuit) isgenerally more advantageous than a circuit design technique usingphysical-characteristic-extracted data at a transistor level.Specifically, standard cells corresponding to logic gates such as aflip-flop, a NAND, an inverter and an AND are registered in a library.Then, a cell-base design combining these standard cells is applied todesign an LSI circuit, thus enabling the LSI circuit to be designed in ashort period.

However, in the case where physical characteristics at the input andoutput vary depending on the state of a clock signal as described above,it is difficult to extract physical characteristics that are to beregistered in a library as those of standard cells. If physicalcharacteristics associated with the respective states of the clocksignal are extracted and registered in the library, different operationsare needed for the respective states of the clock signal during a timingverification of a circuit using such cells, so that processing becomesvery complicated. Therefore, a circuit design using the cell-base designas described above is difficult in reality. In these circumstances, ithas been impossible to design and develop circuits including flip-flopcircuits in short periods.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to keep physicalcharacteristics at input and output terminals of a flip-flop circuitconstant, irrespective of the state of a timing signal such as a clocksignal.

In order to achieve this object, a flip-flop circuit according to thepresent invention includes: an input terminal to which an input signalis input; a master latch portion for holding a signal input from theinput terminal immediately before a timing signal changes from a firststate to a second state, while the timing signal is in the second state;a slave latch portion for holding a signal input from the master latchportion immediately before the timing signal changes from the secondstate to the first state, while the timing signal is in the first state;and an output terminal from which a signal according to a signal held inthe master latch portion is output when the timing signal is in thesecond state and a signal according to a signal held in the slave latchportion is output when the timing signal is in the first state. At leastone of an input capacitance at the input terminal and a drivingcapability at the output terminal when the timing signal is in the firststate is equal to that when the timing signal is in the second state.

With this configuration, a signal input immediately before a timingsignal changes from a first state to a second state is output with ashort delay and, in addition, input capacitance and/or drivingcapability are/is constant irrespective of the state of the timingsignal. Accordingly, the input capacitance and the driving capabilityare easily extracted as those of a standard cell and circuit design iscompleted in a short period.

The flip-flop circuit may include a selecting portion for selecting asignal according to a signal held in the master latch portion or theslave latch portion and outputting the selected signal. The selectingportion may be configured by using tri-state elements which have thesame driving capability in their active states (i.e., in the stateswhere the outputs thereof are not in high-impedance states) and only onewhich is active at a time. Alternatively, the selecting portion may beconfigured by using pass gates only one of which is active at a time anda driver receiving the outputs of these pass gates.

An input signal may be input to, for example, a tri-state element, whichis not an element such as a pass gate whose electrical connecting statechanges, i.e., may be input not to the sources and drains of transistorsconstituting an element, for example, but only to the gates thereof.

If a tri-state inverter or an inverter is used as the tri-state elementor the driver described above, a signal at a desired level is easilyheld and output without the use of additional inverter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a first embodiment.

FIG. 2 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a second embodiment.

FIG. 3 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a third embodiment.

FIG. 4 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a modified example of the third embodiment.

FIG. 5 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a fourth embodiment.

FIG. 6 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a fifth embodiment.

FIG. 7 is a circuit diagram illustrating a configuration of a flip-flopcircuit according to a sixth embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be specificallydescribed with reference to the drawings.

In the following embodiments, components having similar functions aredenoted by the same reference numerals, and the descriptions thereofwill be omitted.

Embodiment 1

FIG. 1 is a circuit diagram illustrating a flip-flop circuit accordingto a first embodiment of the present invention.

A master latch portion 101 includes: a tri-state inverter 111; aninverter 112; and an inverter 113. The master latch portion 101 performslatch operation for allowing data to be written therein when a timingsignal input from a timing signal input terminal 104 is “0” (e.g., at anL level) and holding data when the timing signal is “1” (e.g., at an Hlevel). The inverter 112 has a driving capability lower than that of thetri-state inverter 111.

A slave latch portion 102 includes: a pass gate 114; an inverter 115;and an inverter 116. The slave latch portion 102 holds data when thetiming signal is “0” and allows data to be written therein when thetiming signal is “1”. The inverter 116 has a driving capability lowerthan that of the tri-state inverter 113 connected thereto via the passgate 114.

A bypass 103 is a signal line for outputting data written and held inthe master latch portion 101 such that the data does not pass throughthe slave latch portion 102, thus reducing the delay time, as comparedto a case where the data is output by way of the slave latch portion102.

A data output selecting portion 107 includes: a pass gate 117; a passgate 118; and an inverter 119. The data output selecting portion 107selects one of the output of the slave latch portion 102 and the outputof the bypass 103 according to a timing signal input from the timingsignal input terminal 104 and allows the selected signal to be outputfrom a data output terminal 106. More specifically, the output of theslave latch portion 102 is selected when the timing signal is “0” andthe output of the bypass 103 is selected when the timing signal is “1”.

An inverter 120 generates an inverted signal of a timing signal inputfrom the timing signal input terminal 104.

With the foregoing configuration, data (a signal) input from a datainput terminal 105 is input to a latch constituted by the inverters 112and 113 via the tri-state inverter 111. That is, only the gate terminalsof transistors constituting the tri-state inverter 111 are electricallyconnected to the data input terminal 105 irrespective of the state ofthe timing signal, so that the input capacitance is kept constant.

In both cases where the pass gate 117 conducts and where the pass gate118 conducts, the output signal from the pass gate 117 or 118 is outputto the data output terminal 106 via the inverter 119. That is, thedriving capability of the flip-flop circuit is determined by the drivingcapability of the inverter 119 and, therefore, is kept constantirrespective of the state of the timing signal.

Accordingly, the characteristics of a flip-flop circuit as describedabove are easily extracted so that the flip-flop circuit is used for acell-base deign as a standard cell. The use of a cell library includingthe flip-flop circuit used as such a standard cell enables circuitdesign to be completed in a short period.

Data holding operation of the flip-flop circuit itself is performed inthe same manner as the conventional flip-flop circuit as follows.

When the timing signal is “0”, the master latch portion 101 performsdata writing operation so that a signal input from the data inputterminal 105 is written in the master latch portion 101. The slave latchportion 102 performs data holding operation so that the output of theslave latch portion 102 does not change from the state immediatelybefore the timing signal changes to “0”. The bypass 103 transmits thesignal written in the master latch portion 101 to the data outputselecting portion 107. However, the data output selecting portion 107selects the data output from the slave latch portion 102 and causes theselected data to be output from the data output terminal 106. That is,irrespective of the value input to the data input terminal 105, dataheld in the slave latch portion 102 is continuously output from the dataoutput terminal 106.

On the other hand, when the timing signal transitions from “0” to “1”,the master latch portion 101 shifts from data writing operation to dataholding operation so that the value input to the data input terminal 105immediately before the timing signal transitions from “0” to “1” is heldin the master latch portion 101. The slave latch portion 102 shifts fromdata holding operation to data writing operation and, after the timingsignal has transitioned from “0” to “1”, the output of the master latchportion 101 is written in the slave latch portion 102. The bypass 103transmits the signal held in the master latch portion 101 to the dataoutput selecting portion 107. The data output selecting portion 107shifts from the state of selecting the output of the slave latch portion102 to the state of selecting the signal transmitted from the bypass103. That is, the state where the value held in the slave latch portion102 is output from the data output terminal 106 changes to the statewhere the value input to the data input terminal 105 immediately beforethe timing signal transitions from “0” to “1” is output by way of themaster latch portion 101 and the bypass 103 (i.e., is not output by wayof the slave latch portion 102).

In this manner, the signal is transmitted by way of the bypass 103, sothat the delay time from the rising edge of the timing signal to thetime when the value input to the data input terminal 105 at the risingedge is output from the data output terminal 106 is reduced as comparedto the case where the signal is transmitted by way of the slave latchportion 102.

When the timing signal is “1”, the master latch portion 101 performsdata holding operation, so that the output of the master latch portion101 is unchanged. The slave latch portion 102 performs data writingoperation. However, since the output of the master latch portion 101 asan input does not change, the output of the slave latch portion 102 doesnot change either. The bypass 103 continues to transmit the signal heldin the master latch portion 101 to the data output selecting portion107. The data output selecting portion 107 selects the output of thebypass 103 and outputs the data held in the master latch portion 101 tothe data output terminal 106. That is, irrespective of the value at thedata input terminal 105, data held in the master latch portion 101 iscontinuously output.

When the timing signal transitions from “1” to “0”, the master latchportion 101 shifts from data holding operation to data writingoperation. After the timing signal has transitioned from “1” to “0”, thevalue input to the data input terminal 105 is written in the masterlatch portion 101. The slave latch portion 102 shifts from data writingoperation to data holding operation and the output of the master latchportion 101 immediately before the timing signal transitions from “1” to“0” is written and held in the slave latch portion 102. The bypass 103transmits the signal written in the master latch portion 101. However,the data output selecting portion 107 shifts from the state of selectingthe signal transmitted from the bypass 103 to the state of selecting theoutput of the slave latch portion 102. That is, the value held in themaster latch portion 101 when the timing signal is “1” comes to be heldin the slave latch portion 102 and is selected by the data outputselecting portion 107. Accordingly, the output from the data outputterminal 106 does not change from the state when the timing signal is“1”.

As described above, at the rising edge of the timing signal, flip-flopoperation in which the value input to the data input terminal 105 iswritten and output from the data output terminal 106 is performed. Inaddition, an output is produced at a high speed at the rising edge ofthe timing signal.

Furthermore, the input capacitance and the driving capability are keptconstant as described above, so that circuit design is completed in ashort period with physical characteristics extracted as those of astandard cell.

Embodiment 2

Instead of the master latch portion 101 and the slave latch portion 102including the inverters 112 and 116, respectively, of the firstembodiment, a master latch portion 201 and a slave latch portion 202including tri-state inverters 212 and 216, respectively, may be used asshown in FIG. 2.

The tri-state inverters 212 and a tri-state inverter 111 operate atdifferent states of a timing signal, and the tri-state inverter 216 anda pass gate 114 also operate at different states of the timing signal.Accordingly, the outputs of the tri-state inverter 212 and the tri-stateinverter 111 do not conflict with each other, and the outputs of thetri-state inverter 216 and the pass gate 114 do not conflict with eachother.

With this configuration, holding operation of input data itself is alsothe same as that in the conventional flip-flop circuit, as described inthe first embodiment.

In addition, irrespective of the state of the timing signal, only thegate terminals of transistors constituting the tri-state inverter 111are electrically connected to a data input terminal 105 and the drivingcapability of the flip-flop circuit is determined by the drivingcapability of an inverter 119, so that the input capacitance and thedriving capability are kept constant as in the first embodiment.Accordingly, it is also easy to extract physical characteristics asthose of a standard cell. The use of a cell library including theflip-flop circuit as such a standard cell enables circuit design to becompleted in a short period.

Embodiment 3

Instead of the data output selecting portion 107 of the firstembodiment, a data output selecting portion 307 including tri-stateinverters 317 and 318 may be provided as shown in FIG. 3. When the valueof a timing signal is “0”, the tri-state inverters 317 and 318 selectthe output of a slave latch portion 102 (i.e., the tri-state inverter317 is active and the tri-state inverter 318 is in a high-impedancestate). On the other hand, when the value of the timing signal is “1”,the tri-state inverters 317 and 318 select the output from a bypass 103(i.e., the tri-state inverter 317 is in a high-impedance state and thetri-state inverter 318 is active).

In this embodiment, the tri-state inverters 317 and 318 have the samedriving capability (physical characteristic). Specifically, elements(transistors) constituting these inverters are designed to have the samesize and shape, for example. That is, the driving capability of thetri-state inverter 317 does not affect the response ability when thetiming signal rises and, therefore, the driving capability can be setsmall. However, in this embodiment, the tri-state inverter 317 isintentionally designed to have the same driving capability as that ofthe tri-state inverter 318 so that the driving capability of theflip-flop circuit is unchanged irrespective of which of the tri-stateinverters 317 and 318 is active. This also enables easy extraction ofphysical characteristics as those of a standard cell. The use of a celllibrary including the flip-flop circuit as such a standard cell enablescircuit design to be completed in a short period.

In the case where the tri-state inverters 317 and 318 are used asdescribed above, an output driver such as an inverter 119 or a buffermay be provided between the tri-state inverters 317 and 318 and a dataoutput terminal 106 as shown in FIG. 4, as in the first and secondembodiments. In this case, even if the tri-state inverters 317 and 318have different driving abilities, the driving capability of theflip-flop circuit is kept constant. However, if the tri-state inverters317 and 318 are designed to have the same driving capability and theinverter 119 and other elements are not provided, the flip-flop circuitoperates at a higher speed because of the absence of a delay caused bythe inverter 119 and other elements.

Embodiment 4

An example of a flip-flop circuit usable for, for example, a scanningtest for a semiconductor integrated circuit will be described. As shownin FIG. 5, this flip-flop circuit includes a master latch portion 401including a tri-state selector 430 instead of the master latch portion101 including the tri-state inverter 111 of the second embodiment (FIG.2). An inverted data output terminal 410 is connected to the output of aslave latch portion 202 via serially-connected inverters 431 and 432 soas to output an inverted signal of a signal output from a data outputterminal 106.

The tri-state selector 430 includes PMOS transistors (p-type MOStransistors) 420 through 424 and NMOS transistors (n-type MOStransistors) 425 through 429. When a timing signal is “1”, the output ofthe tri-state selector 430 is in a high-impedance state as the tri-stateinverter 111 of the first and second embodiments. On the other hand,when the timing signal is “0”, the tri-state selector 430 outputs aninverted signal of one of a data signal input from a data input terminal105 and a scanning test signal input from a scanning input terminal 408according to a scanning control signal input from a scanning controlterminal 409 (i.e., operates as a tri-state inverter having a selectingfunction). More specifically, when the scanning control signal is “0”,the tri-state selector 430 operates as the tri-state inverter 111 shownin FIG. 2 and when the scanning control signal is “1”, the tri-stateselector 430 operates in the same manner with respect to a signal inputfrom the scanning input terminal 408.

With this configuration, only the gate terminals of transistorsconstituting the tri-state selector 430 are electrically connected tothe data input terminal 105 and the scanning input terminal 408irrespective of the state of the timing signal, so that the inputcapacitance is kept constant. In addition, since the driving capabilityof the flip-flop circuit is determined by the driving capability of aninverter 119, the driving capability of the flip-flop circuit is alsokept constant irrespective of the state of the timing signal.

The inverted signal output from the inverted data output terminal 410may be generated based on the output of a pass gate 117 or the inverter119 so as to reduce a delay in the same manner as that for an outputsignal from the data output terminal 106. In a case where the speed inoutputting a signal from the inverted data output terminal 410 does notneed to be increased so much as in the case of a scanning test for asemiconductor integrated circuit, for example, this signal can begenerated based on the output of the slave latch portion 202 asdescribed above. This suppresses loads such as a pass gate 118 andeasily ensures a high-speed output of a signal from the data outputterminal 106 without the need for increasing the driving capability.

The output of the inverter 431 may be directly connected to the outputterminal (i.e., without insertion of the inverter 432) so that signalshaving the same logic value are individually output from the inverteddata output terminal 410 and the data output terminal 106. In this case,the signal output from the data output terminal 106 is only used fordriving circuits which need high speed operation whereas the signaloutput from the inverted data output terminal 410 is used for drivingcircuits which do not need especially high speed operation.

Embodiment 5

As shown in FIG. 6, instead of the master latch portion 401 and theslave latch portion 202 of the fourth embodiment, a master latch portion501 and a slave latch portion 502 including a tri-state inverter 512 anda NAND 515, respectively, may be provided to implement a reset function.With this configuration, when a reset signal input from a reset terminal531 transitions to “0”, reset operation in which “0” is output from adata output terminal 106 is performed, as in a conventional flip-flopcircuit having a reset function.

In the foregoing configuration, a data input terminal 105 and a scanninginput terminal 408 are connected to a tri-state selector 430 and thedata output terminal 106 is connected to an inverter 119 as in thefourth embodiment, so that the input capacitance and the drivingcapability are kept constant irrespective of the state of a timingsignal.

Embodiment 6

As shown in FIG. 7, instead of the master latch portion 401 and theslave latch portion 202 of the fourth embodiment, a master latch portion601 and a slave latch portion 602 including a NAND 613 and a tri-stateNAND 616, respectively, are provided to implement a set function. Withthis configuration, when a set signal input from a set terminal 631transitions to “0”, set operation in which “1” is output from a dataoutput terminal 106 is performed as in a conventional flip-flop circuithaving a set function.

With the foregoing configuration, the input capacitance and the drivingcapability are kept constant, irrespective of the state of a timingsignal, as in the fifth embodiment and other embodiments.

In the foregoing embodiments, examples of a flip-flop circuit operatingat the rising edge of a timing signal have been described.Alternatively, a flip-flop circuit operating at a falling edge may beconfigured. Specifically, a signal input from the timing signal inputterminal 104 and a signal inverted by the inverter 120 from the signalinput from the timing signal input terminal 104 may be replaced witheach other, for example.

To control the tri-state inverter 111 and other elements, a timingsignal input from the timing signal input terminal 104 and a signalinverted by the inverter 120 from the timing signal are used as anexample. However, the present invention is not limited to this. A signalinverted by the inverter 120 from the timing signal input from thetiming signal input terminal 104 and a further-inverted signal thereofmay be used, for example.

In the foregoing embodiments, a signal having the same logic value asthat of the signal input from the data input terminal 105 when thetiming signal rises is output from the data output terminal 106.Alternatively, a signal having an inverted logic value thereof may beoutput. Specifically, instead of the tri-state inverter 111, theinverter 119 and tri-state selector 430 for an inverted output, forexample, a tri-state buffer, a buffer and a tri-state selector for anon-inverted output may be used or an odd number of inverters may beinserted.

As an element connected to the data input terminal 105, an elementhaving a function as an inverter or an element having a function as abuffer may be used to make the input capacitance constant irrespectiveof the state of a timing signal as long as the data input terminal 105is connected only to the gates of transistors constituting the element.

As described in the modified example of the fourth embodiment, aninverted signal having a small delay may be output based on the outputof one of the pass gate 117 and the inverter 119 or a signal having thesame logic value as that of a signal output from the data outputterminal 106 may be output based on the output of the slave latchportion 102, in the fifth and sixth embodiments. In the first throughthird embodiments, a signal having the same logic value as that of asignal output from the data output terminal 106 and having a small delayor a signal having the same or inverted logic value and having arelatively large delay may be output in the same manner.

In the fifth or sixth embodiment, the reset state or the set state isestablished when a signal at the reset terminal 531 or the set terminal631 is “0”. However, the present invention is not limited to this, andthe reset state or the set state may be established when the signal is“1”.

In addition, components of the foregoing embodiments and modifiedexamples may be variously combined in an allowable range. Specifically,the data output selecting portion 307 including the tri-state inverters317 and 318 of the third embodiment (FIG. 3) may be applied to theconfiguration of the second embodiment (FIG. 2) in which the masterlatch portion 201 and the slave latch portion 202 including thetri-state inverters 212 and 216, respectively, are used. Alternatively,the configurations of the fifth and sixth embodiments (FIGS. 6 and 7)may be combined together to configure a flip-flop circuit enabling bothreset and set. The configuration enabling reset and/or set may beapplied to the configurations of the first through third embodiments.

The flip-flop circuit including no bypass as described above may beconfigured by using a tri-state element, for example, at the input ofthe master latch portion such that the input capacitance does not dependon a timing signal.

As described above, the flip-flop circuit according to the presentinvention has an advantage in which physical characteristics at theinput and output terminals of the flip-flop circuit are kept constantirrespective of the state of a timing signal such as a clock signal.This flip-flop circuit is useful as a flip-flop circuit constituted bytransistors formed as a semiconductor integrated circuit, for example.

1. A flip-flop circuit, comprising: an input terminal to which an inputsignal is input, a master latch portion for holding a signal input fromthe input terminal immediately before a timing signal changes from afirst state to a second state, while the timing signal is in the secondstate; a slave latch portion for holding a signal input from the masterlatch portion immediately before the timing signal changes from thesecond state to the first state, while the timing signal is in the firststate; and an output terminal from which a signal according to a signalheld in the master latch portion is output when the timing signal is inthe second state and a signal according to a signal held in the slavelatch portion is output when the timing signal is in the first state,wherein at least one of an input capacitance at the input terminal and adriving capability at the output terminal when the timing signal is inthe first state is equal to that when the timing signal is in the secondstate.
 2. The flip-flop circuit of claim 1, wherein both of the inputcapacitance at the input terminal and the driving capability at theoutput terminal when the timing signal is in the first state are equalto those when the timing signal is in the second state.
 3. The flip-flopcircuit of claim 2, wherein circuit characteristics are extracted asthose of a standard cell for use in a cell-base design.
 4. The flip-flopcircuit of claim 2, further comprising a selecting portion for selectinga signal according to a signal held in the master latch portion when thetiming signal is in the second state, selecting a signal according to asignal held in the slave latch portion when the timing signal is in thefirst state, and causing the selected signal to be output from theoutput terminal.
 5. The flip-flop circuit of claim 4, wherein theselecting portion includes: a first tri-state element for outputting asignal according to a signal held in the master latch portion when thetiming signal is in the second state and setting an output thereof in ahigh-impedance state when the timing signal is in the first state; and asecond tri-state element for outputting a signal according to a signalheld in the slave latch portion when the timing signal is in the firststate and setting an output thereof in a high-impedance state when thetiming signal is in the second state, wherein the outputs of the firstand second tri-state elements are connected to the output terminal, anda driving capability of the first tri-state element when the timingsignal is in the second state is equal to that of the second tri-stateelement when the timing signal is in the first state.
 6. The flip-flopcircuit of claim 5, wherein the first and second tri-state elements aretri-state inverters.
 7. The flip-flop circuit of claim 4, wherein theselecting portion includes: a first tri-state element for outputting asignal according to a signal held in the master latch portion when thetiming signal is in the second state and setting an output thereof in ahigh-impedance state when the timing signal is in the first state; asecond tri-state element for outputting a signal according to a signalheld in the slave latch portion when the timing signal is in the firststate and setting an output thereof in a high-impedance state when thetiming signal is in the second state; and a driver for receiving outputsignals from the first and second tri-state elements and outputting asignal to the output terminal.
 8. The flip-flop circuit of claim 7,wherein the first and second tri-state elements are tri-state inverters.9. The flip-flop circuit of claim 7, wherein the driver is an inverter.10. The flip-flop circuit of claim 4, wherein the selecting portionincludes: a fist pass gate that conducts and outputs a signal accordingto a signal held in the master latch portion when the timing signal isin the second state, and sets an output thereof in a high-impedancestate when the timing signal is in the first state; a second pass gatethat conducts and outputs a signal according to a signal held in theslave latch portion when the timing signal is in the first state, andsets an output thereof in a high-impedance state when the timing signalis in the second state; and a driver for receiving output signals fromthe first and second pass gates and outputting a signal to the outputterminal.
 11. The flip-flop circuit of claim 10, wherein the driver isan inverter.
 12. The flip-flop circuit of claim 2, wherein a gate of anidentical transistor is electrically connected to the input terminalboth when the timing signal is in the first state and when the timingsignal is in the second state.
 13. The flip-flop circuit of claim 2,wherein the master latch portion is a tri-state element controlledaccording to the timing signal, and the input terminal is connected tothe tri-state element.
 14. The flip-flop circuit of claim 13, whereinthe tri-state element is a tri-state inverter.
 15. The flip-flop circuitof claim 1, wherein at least one of operation of resetting the state ofholding a signal according to a reset signal and operation of settingthe state of holding a signal according to a set signal is performed.16. The flip-flop circuit of claim 1, further comprising another inputterminal, wherein a signal is held based on a signal input to one of theinput terminals, according to a switching control signal.
 17. Aflip-flop circuit, comprising: a data input terminal; a data outputterminal; a master latch portion; a slave latch portion; a bypass; and adata output selecting portion, wherein the master latch portion includesa first tri-state inverter, a first inverter and a second tri-stateinverter, the first tri-state inverter is in a high-impedance state whena given timing signal is in a first state and outputs an inverted signalof a signal input from the data input terminal when the timing signal isin a second state, the first inverter outputs an inverted signal of anoutput of the first tri-state inverter, the second tri-state inverter isin a high-impedance state when the timing signal is in the second stateand outputs an inverted signal of an output of the first inverter to thefirst inverter when the timing signal is in the first state, the slavelatch portion includes a first pass gate, a second inverter and a thirdtri-state inverter, the first pass gate is in a high-impedance statewhen the timing signal is in the second state and allows an output ofthe first inverter to pass through when the timing signal is in thefirst state, the second inverter outputs an inverted signal of an outputof the first pass gate, the third tri-state inverter is in ahigh-impedance state when the timing signal is in the first state andoutputs an inverted signal of an output of the second inverter to thesecond inverter when the timing signal is in the second state, thebypass transmits an output of the first tri-state inverter withoutchange, the data output selecting portion includes a second pass gate, athird pass gate and a third inverter, the second pass gate is in ahigh-impedance state when the timing signal is in the first state andallows an output of the second inverter to pass through when the timingsignal is in the second state, the third pass gate is in ahigh-impedance state when the timing signal is in the second state andallows an output of the first tri-state inverter to pass through whenthe timing signal is in the first state, and the third inverter receivesoutputs of the second and third pass gates and outputs an invertedsignal of each of the outputs to the data output terminal.
 18. Theflip-flop circuit of claim 17, wherein the first tri-state inverter is atri-state selector that is in a high-impedance state when the timingsignal is in the first state and outputs, according to a given selectionsignal, an inverted signal of a signal input from the data inputterminal or another data input terminal when the timing signal is in thesecond state.
 19. The flip-flop circuit of claim 18, wherein the secondtri-state inverter is a tri-state logic gate element that is in ahigh-impedance state when the timing signal is in the second state andoutputs, according to a given reset signal, an inverted signal of anoutput of the first inverter or a signal at a level enough to set themaster latch portion in a reset state to the first inverter when thetiming signal is in the first state, and the second inverter is a logicgate element that outputs, according to the reset signal, an invertedsignal of an output of the first pass gate or a signal at a level enoughto set the slave latch portion in a reset state.
 20. The flip-flopcircuit of claim 18, wherein the first inverter is a logic gate elementthat outputs, according to a given set signal, an inverted signal of anoutput of the tri-state selector or a signal at a level enough to setthe master latch portion in a set state, and the third tri-stateinverter is a tri-state logic gate element that is in a high-impedancestate when the timing signal is in the first state and outputs,according to the set signal, outputs an inverted signal of an output ofthe second inverter or a signal at a level enough to set the slave latchportion in a set state to the second inverter when the timing signal isin the second state.